1. Field of the Invention
The present invention is in the field of integrated circuits, and is particularly directed to fuse circuits with feedback.
2. Description of the Prior Art
Many types of semiconductor memories are containing greater numbers of storage locations and higher capacity as manufacturing technology improves. For example, static random access memories (SRAMs) having 2.sup.20 storage locations (i.e., 1 Mbits) and dynamic random access memories (DRAMs) having 2.sup.22 storage locations (i.e., 4 Mbits) are available in the market. Additional highdensity memories include FIFOs, dual-port memories, and read-only memories of various types, fabricated as individual components and embedded in other integrated circuits such as microprocessors and other logic devices. These high-density memories, however, are usable only if each and every storage location or "bit" can be accessed and store both digital data states. Failure of a single storage location, or bit, may cause the entire memory (and logic device having an embedded memory) to be non-marketable, thereby increasing manufacturing costs and decreasing yields.
As a result, many semiconductor memories are now fabricated with redundant rows or columns which, when enabled, replace an entire row or column in the primary memory array. For example, a chip may contain two redundant rows for each subarray which may be substituted for defective rows. In this case, only chips with three or more defective rows in a subarray will be discarded. Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51.
The enabling of redundant architecture is conventionally done during the manufacturing test process, where the primary memory is tested for functionality of the bits. The addresses of failing bits are logged, and an algorithm in the automated test equipment determines if the redundant rows or columns available on the circuit are sufficient to replace all of the failing bits. If so, fuses are opened (or, alternatively, anti-fuses may be closed) in the decoding circuitry of the memory so that the failing row or column is no longer enabled by its associated address value. Instead, access is made to the spare row or column upon receipt of the address for the defective row or column in the primary memory array. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses.
Conventional fuse circuitry, however, has not been entirely satisfactory when used in integrated circuit devices. Fuse circuitry frequently requires a latching function right at the fuse location. Due to the latching and resultant feedback path, the state of the circuitry near the fuse can be indeterminate when the fuse is blown. Indeterminate states within integrated circuits can result in parts which are unreliable or unstable. For example, this problem arose in the design of the fast cache SRAM memory device. The use of conventional fuse circuitry to disable defective rows or columns could not reliably maintain the output at the proper logic level. The problem was attributed to the circuitry feedback.
Therefore, it would be desirable to have a method and circuit for reliably setting the output of the circuit to a desired logic state, thereby preventing the feedback path from adversely affecting the output.